Substrates usefull in manufacturing semiconductor devices are increasingly required to possess a higher degree of freedom when designing a device to be fabricated thereon. Therefore, this trend has drawn more attention to the substrates of so called SOI type, which typically comprise a bonded wafer being structured such that a thermally grown oxide layer is sandwiched between two silicon wafers, at least one of the silicon wafers being mono-crystalline. The bonded wafer may be used for making an electric device such as a semiconductor device or, for example, a micro machine in one of the other fields of application. A transistor built on the SOI has an advantage of requiring low supply voltage and low operation voltage due to reduced well and load resistance. In addition, the SOI transistor exhibits high operation speed.
However, the SOI transistor has some inherent drawbacks. One important shortcoming of these SOI transistors is the occurrence of the floating body effect, or electrical floating. The electrical floating of the transistor active region allows the unstable characteristics of the transistors and generates reliability concerns associated with transistor mis-operation and degradation of the characteristics.
FIG. 1 schematically illustrates a DRAM device built on an SOI. The DRAM device typically includes a reversed capacitor 20 and word lines 14a and 14b, respectively formed on first insulating layer 22 and second insulating layer 18 which are disposed over a handling wafer 24 in this order. A device isolation layer 12 defines an active and an inactive region. The reversed capacitor 20 is connected to one of the source/drain regions 16 through the second insulating layer 18. The other of the source/drain regions 16 is connected to a bit line 28 at a selected portion while other areas are insulated from the other source/drain regions 16 by a third insulating layer 26 formed therebetween. An area underlying the word line 14a and between the pair of the source/drain regions 16 is defined as a channel area. A fourth insulating layer 30 is disposed over the bit line 28 and metal lines 30a and 30b are formed on the fourth insulating layer 30.
As can be seen, the channel area is in the state of electrical floating. Such a floating state of the channel area allows an irregular variation of the threshold due to an accumulation hole. Thus, there exists a need to develop a semiconductor memory device having an SOI structure that does not suffer from the drawbacks associated with electrical floating.